Synaptics launches Astra SR200 xMCU with 400 GOPS Coral NPU from Google Research

Microcontrollers are the least glamorous layer of the computing stack, and for most of their history they have been defined by what they cannot do. A typical part pairs a modest processor core with a few hundred kilobytes of on chip memory, enough for motor control, sensor polling or a simple display, but nowhere near enough to host a modern neural network. Edge AI has therefore meant either a small model squeezed into an MCU or a jump to microprocessor class silicon that draws far more power. That trade off is what Synaptics and Google Research set out to attack.

Google Research has spent the past several years developing an open neural processing unit called Coral NPU, with the goal of making on device machine learning portable across chip vendors. The project started with a RISC-V based front end, which Google calls its first milestone, and has grown into a full architecture with an open compiler stack. The pitch is straightforward: a model trained once in JAX, PyTorch or TensorFlow should run on any silicon that implements the architecture, without a proprietary toolchain in the path.

On October 20, 2026, Synaptics launched the Astra SR200 series at its Tech Day in San Jose, California, and branded the devices xMCUs, a new class of microcontroller aimed at multimodal edge AI. The flagship SR250 pairs an Arm Cortex-M85 running at 800 MHz with a Cortex-M52 efficiency core at 200 MHz and a 400 GOPS Torq NPU built on Google Research's second-generation Coral NPU design. Synaptics says the family targets AI wearables, battery powered sensing devices, connected cameras, streamers and industrial vision and voice systems.

The launch came bundled with three architecture announcements from Google Research. The Google Developers Blog reported on October 20 that the company had completed the full 32-bit Coral NPU architecture across milestones one through four, shipped Coral Compiler v1.0 as an open source end to end IREE and MLIR compiler and simulation stack, and unveiled the Astra SR200 as the second commercial chip built on Coral NPU.

Key Facts

Synaptics said in a press release distributed by GlobeNewswire on October 20 that the SR200 is powered by the Torq AI engine featuring the Coral NPU from Google Research, and that the family introduces the industry's first pairing of Arm Cortex-M85 and Cortex-M52. Three pin compatible parts share one hardware foundation and one software development kit. The SR210 runs a Cortex-M85 at 400 MHz with 4MB of SRAM plus a Cortex-M52 at 100 MHz with 1MB, and delivers 200 GOPS for consumer sensor hubs, smart doorbells and thermostats. The SR230 moves to 600 MHz and 5MB plus 150 MHz and 1.5MB, with 300 GOPS and an optional Cadence Tensilica HiFi 5 DSP, aimed at smartwatches, smart sensors and cameras. The SR250 runs at 800 MHz and 6MB plus 200 MHz and 2MB, with 400 GOPS and dual vision and display paths, for premium AR/VR glasses, robotics and industrial control.

All three parts use an identical flip chip BGA package layout, so a designer can carry a single board schematic across the range and change compute headroom without relaying out the board. Memory is the other half of the story: Synaptics pairs up to 8MB of on chip SRAM with an integrated custom DRAM that scales to hundreds of megabytes. The company claims this runs workloads at one third the power of typical system DRAM and removes the need for costly external memory in most applications, a detail that matters because transformer models run out of memory long before they run out of compute.

Synaptics reported in a product blog published on October 20 that the Torq NPU was co-developed closely with Google Research and is the first microcontroller class NPU with native bfloat16 precision alongside INT8 and INT16. The block carries 256 MAC units, 256KB of local RAM and a RISC-V vector core, and is designed to run both convolutional networks and modern transformers without re-spinning silicon. Google's description of the second generation Coral NPU adds that the Matrix Execution Unit is configurable up to 1 TOPS, targets 10 mW average power for inference, and follows the RISC-V VME specification's Zvt family with a dedicated outer product multiply accumulate engine that computes a full 2D tile in a single cycle at 256 MACs per cycle. Google also said VeriSilicon handled design implementation and verification, while GlobalFoundries 12LP+ FinFET work accelerated core timing by 70% and cut standard cell area by up to 15% across RTL iterations.

Software is where the two companies are making their most explicit bet. Coral Compiler v1.0 ingests PyTorch, ONNX, JAX and TensorFlow Lite models and lowers Torch-mlir, StableHLO and TOSA dialects to Linalg, Tensor and Math before emitting bytecode for the Torq engine, the Coral NPU, the GPU or host CPUs; Synaptics said the toolchain was built on MLIR and IREE specifically to avoid proprietary compiler lock-in, and R&D World reported on October 16 that the open source compiler took about 18 months to develop. On efficiency, R&D World reported on October 16 that Avinatan Hassidim, a vice president of Google Research, said the M2 Coral design uses 40% less energy than other processors on the market and runs on device inference at an average draw of less than 6 milliwatts, though the article noted that he did not specify workloads or comparison processors, making the figure a vendor claim. The complete 32-bit RTL is published on GitHub under google-coral/coralnpu.

Analysis

The first thing to say is that Synaptics has not simply added a faster accelerator to an existing microcontroller line. What this really means is that the company is trying to move the boundary between MCU and microprocessor, and it is doing so with an outside architecture rather than a homegrown one. The 400 GOPS part, the DRAM scaling to hundreds of megabytes and the shared package layout together describe a family that competes as much with application processors inside smart cameras and wearables as with conventional microcontrollers.

The bigger picture here is that the competitive axis in embedded AI has shifted from raw arithmetic throughput to memory capacity and software portability. A 400 GOPS NPU is only useful if weights and activations can live close by, which is why the custom DRAM matters more than the headline number. Equally, a compiler that accepts PyTorch, JAX, ONNX and TensorFlow Lite and targets four different execution units removes the biggest recurring cost in embedded machine learning, which is re-porting a model every time the silicon changes.

There is a strategic asymmetry worth naming. Synaptics gets a credible AI story and the first pairing of Cortex-M85 and Cortex-M52, but the defining block, the NPU, belongs to Google Research, and the compiler belongs to the open source community. That is a good trade for a mid-sized chip company that cannot fund an instruction set, a compiler team and a developer ecosystem alone, but it means Synaptics differentiates on integration, memory design and time to market rather than on proprietary silicon. Google, meanwhile, gains another commercial implementation of its architecture, which is how open standards acquire gravity.

The caution is that none of the efficiency claims have been independently verified. A 40% energy advantage over unspecified competitors and an average inference draw under 6 milliwatts are exactly the sort of figures that need a benchmark harness and a named workload before designers plan a product around them. The architecture is open and the RTL is public, which helps, but openness is not the same as measured performance.

Why It Matters

For device makers, the practical consequence is that a single model now spans power classes. The same compiled artifact can run on a milliwatt class wearable built around the SR210 and on a 1 TOPS Coralboard SL board, which collapses the number of software variants a team must maintain. Google argues that a dedicated matrix engine inside a sub 10 milliwatt envelope is what allows continuous multimodal workloads, including compact transformers such as Gemma, real time voice translation on wearables, spatial audio filtering on hearables and low latency visual perception on robots.

For the wider industry, the launch tests whether an open NPU architecture can attract enough commercial implementations to matter. Google previously partnered with Qualcomm in 2023 on a RISC-V wearable platform for Wear OS, and Coral NPU is a more ambitious attempt at the same problem, because it specifies the compute engine and the compiler rather than a single board. If the SR200 sells, the argument that edge AI requires a fragmented market of proprietary designs weakens.

For developers, the significance is subtler but durable. Microcontroller toolchains have historically been walled gardens, and the Cortex-M85 plus Cortex-M52 combination on the SR200 runs alongside an NPU whose compiler is built on MLIR and IREE, both open projects. Whether or not a team chooses Synaptics, a documented, open path from a PyTorch checkpoint to a 400 GOPS part changes what is reasonable to propose in a product plan.

Next Up

Google said the next design, M3, is complete and adds native 32-bit floating point support, enough to run Gemma 3 270M, a 270-million-parameter model. Neither company gave a shipping date for M3 silicon, so the near term roadmap stops at the SR200 family and its 400 GOPS ceiling.

In the meantime, Synaptics is shipping. The Astra SR200 series has taped out, the Coralboard SR developer kit accompanies the launch, and the 1 TOPS Coralboard SL reached general availability worldwide through DigiKey on October 20, following its limited edition preview at Google I/O. Synaptics CEO Rahul Patel said on October 14 at Google Research's Research@ event in Mountain View that the chip will find its way into Google devices, without naming products or ship dates.