Samsung to use TSMC 3nm process for Nvidia NVHBM base dies, a first at HBM stage

For most of the past decade, Samsung Electronics treated high bandwidth memory as an end to end business. The company fabricated the core die that stores data, built the base die that routes traffic in and out of the stack, and packaged the finished product itself. That turnkey model was a point of pride. It let Samsung control cost, yield and schedule inside one of the most demanding product categories in the semiconductor industry, and it kept the most valuable engineering knowledge in house.

Nvidia's next generation custom memory has forced a rethink of that approach. The base die, a thin layer of logic silicon at the bottom of each HBM stack, is no longer a simple interface between memory and processor. Under Nvidia's NVHBM architecture, unveiled in August, the memory controller moves off the GPU and into the base die. Packing a controller and a shrunken input and output physical layer into that small piece of silicon requires an ultra fine logic process rather than a conventional memory process.

Seoul Economic Daily reported on October 18 that Samsung Electronics will use TSMC's 3 nanometre process to produce the base die for Nvidia's next generation custom high bandwidth memory, known as NVHBM. According to the newspaper, this would mark the first time Samsung has worked with the Taiwanese contract chipmaker at the HBM manufacturing stage. Reuters reported on October 18 that the same Seoul newspaper had documented the plan, citing industry sources.

The shift matters because Samsung and TSMC are direct rivals in the foundry business, the market where companies are paid to manufacture chips designed by others. Samsung has spent years trying to close the gap with TSMC in advanced logic nodes, and here it is handing a piece of its own memory roadmap to the competitor it is chasing. The reason is not sentiment but physics and yield. The new base die must carry functions that used to sit on the graphics processor, and the only practical way to make it at scale today is on TSMC's 3 nanometre lines.

Key Facts

Nvidia has asked the three suppliers tapped to build NVHBM, Samsung Electronics, SK hynix and Micron Technology, to manufacture the base die using TSMC's 3 nanometre process, Seoul Economic Daily reported on October 18. The same report said Nvidia also requested that the core die, the part that actually stores data, be standardised on the sixth generation DRAM process known as 1c. Nvidia made the request because differing manufacturing methods across memory suppliers make it difficult to deliver consistent performance from a single design.

NVHBM integrates Nvidia's custom memory controller into the base die and is aimed at standardising implementation across multiple memory suppliers. According to Nvidia, the design delivers up to 30 percent greater memory bandwidth and 15 percent lower HBM power consumption than standard HBM4E, the seventh generation of the standard. It also frees up as much as 25 percent more area on the compute die, and a customised input and output physical layer reduces the package area occupied by that interface by as much as 67 percent.

The technical demands are severe. Seoul Economic Daily reported on October 18 that the base die sits at the bottom of the HBM stack and consists of logic circuits that determine data transfer speed. To make room for the relocated memory controller, the physical layer was shrunk by 60 percent compared with standard HBM. The industry estimates TSMC's 3 nanometre yield at more than 90 percent, against roughly 60 percent for Samsung Foundry's comparable 2 nanometre SF2 process.

Supply and demand are pushing in the same direction. Investment bank UBS projects HBM demand next year at about 61.5 billion gigabits, a 91 percent increase from this year, while new shipments from memory makers are expected to reach only 54.6 billion gigabits. That leaves a supply shortfall of roughly 10 percent against demand. TrendForce reported on October 9 that Micron has said both its NVHBM and its JEDEC standard HBM4E will use base dies manufactured by an external foundry, and that SK hynix already uses TSMC's 12 nanometre logic process for its HBM4 base die.

Analysis

Samsung's decision is best read as a concession to a customer that has enough leverage to redraw the supply chain. Nvidia is co-designing the NVHBM base die with Samsung Electronics and TSMC, and it wants one design that behaves the same way regardless of which memory maker ships it. That goal is incompatible with three different base die processes running at three different fabs. By insisting on TSMC's 3 nanometre node and the 1c DRAM process for the core die, Nvidia is compressing variability out of a component that sits on the critical path of its AI accelerators.

The bigger picture here is that HBM has stopped being a memory product in the traditional sense and has become a logic product with a memory array attached. The base die now hosts the memory controller, a piece of the system that used to belong to the GPU vendor. Whoever builds that die controls a strategic chokepoint, and right now that is TSMC. Samsung can still make the core die, where its 1c DRAM lines at Hwaseong and Pyeongtaek are the relevant asset, but the logic half of the stack is being outsourced for this particular customer.

Seoul Economic Daily reported on October 18 that Samsung accepted Nvidia's requirements after an internal review by its Device Solutions division. The company plans to retain its in house production model for standard HBM and for custom products supplied to other customers, including AMD, applying its own 4 nanometre foundry process to the base die of HBM4 and HBM4E. That is a deliberately narrow exception rather than a wholesale retreat from the turnkey model. It also explains why the company is assessing whether its own foundry could produce NVHBM base dies if demand exceeds TSMC's capacity, according to the newspaper.

For Nvidia, consolidating base die production at TSMC is the stable choice. TSMC said at its third quarter earnings briefing that it would add two new 3 nanometre production lines at Fab 18 in Tainan, with mass production beginning in the first half of next year and the first half of the year after next. Samsung's 4 nanometre base die lines, by contrast, are located only at Hwaseong Line 17 and part of Pyeongtaek P3, a footprint that is small relative to the volumes NVHBM could require.

Why It Matters

The collaboration marks the second time Samsung and TSMC have worked together around HBM, but the first at the manufacturing stage. Seoul Economic Daily reported on October 18 that the two companies worked together four years ago to ensure compatibility with TSMC's packaging process when connecting HBM to GPUs. That was an interface problem. This is a production problem, and it puts a rival's process inside Samsung's own memory stack.

The competitive read across is uncomfortable for Samsung Foundry. TrendForce reported on October 9 that Samsung is pursuing a dual track strategy for custom HBM such as NVHBM, pairing its HBM core dies with base dies made by either Samsung Foundry or TSMC depending on customer requirements. The yield gap between TSMC's 3 nanometre node at more than 90 percent and Samsung's SF2 2 nanometre node at roughly 60 percent explains why customers with demanding designs are willing to pay for the safer option.

The demand picture raises the stakes further. A projected shortfall of about 10 percent between 61.5 billion gigabits of HBM demand and 54.6 billion gigabits of expected supply next year means every qualified base die is valuable. Nvidia is not simply choosing a vendor. It is assembling a supply chain that can scale without a single memory maker's internal fab becoming the bottleneck.

Next Up

The immediate question is capacity. Samsung has left open the possibility of using its own foundry for NVHBM base dies as a hedge if demand exceeds TSMC's available capacity, and the two new 3 nanometre lines at Fab 18 in Tainan will not reach mass production until the first half of next year and the first half of the year after next. Until then, any surge in NVHBM orders will test how quickly TSMC can convert wafers.

Competitors are moving in parallel. Micron has already said its NVHBM and JEDEC standard HBM4E will use externally manufactured base dies, while SK hynix continues to build HBM4 base dies on TSMC's 12 nanometre logic process. Amazon's Annapurna Labs is set to adopt NVHBM for its next generation Trainium 4 AI accelerator, which means the base die decisions made this year will shape the memory supply chain for several product generations to come.