NVIDIA Trims Vera Rubin HBM4 and NVLink Specs as First NVL72 Racks Reach General Availability

When NVIDIA unveiled Vera Rubin at GTC 2026, the headline numbers were unambiguous: 288 GB of HBM4 per GPU at 22 TB/s, paired with 3.6 TB/s of sixth generation NVLink scale up bandwidth. Those figures anchored comparisons with AMD and the capacity plans of cloud operators. As the first production systems reach customers, the shipping specification reads differently: 19.2 TB/s of HBM4 and 3.0 TB/s of NVLink 6 per GPU. The architecture has not changed. The promises attached to it have.

The timing matters. In the fourth quarter of 2026, NVIDIA and its partners are in the middle of the Vera Rubin ramp, with hyperscalers taking delivery of some of the first NVL72 racks and making them generally available. Oracle Cloud Infrastructure said on October 27 that Vera Rubin NVL72 and Vera CPUs were generally available on OCI, the first cloud to use that label for the platform. Google Cloud has had a single live customer on Rubin powered A5X instances since October 21, with broader general availability planned for November.

The revision arrived without a press release. IT Home spotted in September that NVIDIA had posted updated specifications on its product pages and architecture datasheet, and specialist outlets documented the change as the ramp progressed. NVIDIA had called those numbers preliminary and subject to change. Capacity stays at 288 GB of HBM4 across eight 36 GB stacks, and compute stays at 50 PFLOPS of NVFP4 inference and 35 PFLOPS of NVFP4 training. What moved was bandwidth, on the memory side and across the scale up fabric.

NVIDIA says nothing material has changed for buyers. A representative told Wccftech that the revised figures better reflect systems in volume production and do not affect performance, citing third party agentic benchmarks run on production specifications. That will be tested: customers now receiving hardware bought bandwidth on the strength of the earlier numbers.

Key Facts

ServeTheHome reported on October 31 that per GPU HBM4 fell from 22 TB/s to 19.2 TB/s by dropping pin speed from 10.75 Gbps to 9.375 Gbps, while NVLink scale up bandwidth fell from 3.6 TB/s to a flat 3.0 TB/s, a 600 GB/s or 17% reduction. Capacity held at 288 GB and compute held at 50 PFLOPS NVFP4 inference. The change was not uniform: scale out networking across the NVL72 rose from 28.8 TB/s to 32.4 TB/s, or from 400 GB/s to 450 GB/s per GPU.

TechPowerUp reported on October 26 that NVIDIA reduced HBM4 pin speed from 11.7 Gbps to 9.6 Gbps and lowered its NVLink Nyquist target from 56 GHz to 47 GHz. A lower Nyquist frequency eases demands on the SerDes, cables and board materials, improving yields at the cost of peak bandwidth. Per GPU NVLink is now 1.5 TB/s unidirectional, down from 1.8 TB/s, and the 72 GPU rack carries 1,400 TB/s of memory bandwidth, down from 1,580 TB/s.

TrendForce reported on October 27 that an archived September 1 version of the specification sheet listed the NVL72 at 20.7 TB of HBM4 and 1,580 TB/s, with each GPU at 288 GB and 22 TB/s. The current 1,400 TB/s is a loss of 180 TB/s, about 11.4%, and aggregate NVLink falls from 260 TB/s to 216 TB/s. TrendForce put the per GPU cut at roughly 13% and the NVLink cut at 17%, and noted that Vera CPU memory changed from a fixed 1.5 TB of LPDDR5X to 'up to 1.5 TB.'

HGX Rubin NVL8 took the largest reduction. ServeTheHome reported on October 31 that its HBM4 capacity falls from 2.3 TB to 2.0 TB, bandwidth from 176 TB/s to 130 TB/s, about 26%, NVLink switch bandwidth from 28.8 TB/s to 24 TB/s, NVFP4 training from 280 to 270 PFLOPS and FP8 training from 140 to 130 PFLOPS. A 2.0 TB NVL8 leaves roughly 250 GB per GPU, so only seven of eight HBM4 stacks are populated.

Suppliers were not the binding constraint. TrendForce reported on October 27 that Samsung and SK hynix have disclosed HBM4 at 11.7 Gbps per pin, with Samsung citing a maximum of 13 Gbps, and Micron reports more than 11 Gbps. That is about 3.0 TB/s per stack for Samsung and SK hynix and above 2.8 TB/s for Micron. Hitting 22 TB/s with eight stacks would need roughly 10.7 Gbps per pin, against about 9.4 Gbps for the revised figure, so the ceiling sits in NVIDIA's package and signaling design or in qualification economics.

Analysis

What this really means is that NVIDIA chose to ship the platform rather than the slide. The reductions are modest in isolation, 12.7% on memory bandwidth and 16.7% on NVLink by the updated sheet, but they land on the two axes that decide how well a rack serves large mixture of experts models: how fast weights stream from HBM, and how fast experts cross the scale up domain. A 17% cut to NVLink changes nothing at small scale. It changes how much tensor parallelism one NVL72 can absorb before a cluster reaches for scale out networking, a decision customers make months before deployment.

The technical explanation is more credible than a marketing one. Signal integrity at these rates is unforgiving: faster pins narrow the timing window and strain connectors and substrates. Dropping Nyquist from 56 GHz to 47 GHz, as TechPowerUp reported on October 26, buys margin across the whole link, and margin separates a demo from a rack shippable in tens of thousands of units. Because Samsung, SK hynix and Micron all disclosed parts capable of the original rate, the shortfall points inward, to NVIDIA's memory controller and package design, or to a deliberate choice to qualify more suppliers.

Wccftech reported on October 29 that NVIDIA argues component specifications do not determine application performance, and that system level co-design across models, software, compute, networking and memory is where gains come from. The company says Vera Rubin NVL72 is in full production and shipping today, with 30x more performance per watt and 30x more tokens per dollar than GB300 NVL72, measured in third party agentic benchmarks from AgentX with SemiAnalysis and AgentPerf with Artificial Analysis. Those claims may hold. They are also unfalsifiable at the component level, which is why buyers track the datasheet.

The competitive picture is less forgiving. TechPowerUp reported on October 26 that AMD's Instinct MI455X offers 432 GB of HBM4 per GPU at 23.3 TB/s, and that a 72 GPU Helios rack aggregates roughly 31 TB of memory and about 1.67 PB/s, against roughly 20.7 TB and 1.4 PB/s on Vera Rubin NVL72. AMD's UALoE delivers 3.6 TB/s bidirectional per GPU, 260 TB/s aggregate, against NVIDIA's reduced 3.0 TB/s and 216 TB/s. On paper, AMD now leads on capacity and bandwidth in rack scale systems.

Why It Matters

Procurement teams re-baseline around shipping numbers, not launch numbers. Operators sizing a multi gigawatt build need to know how many racks a training job requires, and memory bandwidth per GPU feeds the arithmetic for model parallelism, batch size and achievable tokens per second. A 12.7% cut per GPU and 11.4% per rack are small enough that no contract reopens, but large enough to shift the answer for a model already close to a capacity boundary.

The episode also marks a change in how NVIDIA sells. For two generations it led with per component superlatives. The revision, and the statement that individual component specifications do not determine application performance, moves the argument to named models and data center scale benchmarks. That is a more defensible position for a systems vendor, but it concedes that the datasheet is no longer the scoreboard. Every future launch should expect the same audit.

For the memory supply chain the revision is arguably good news. TrendForce reported on October 27 that lowering the bandwidth requirement could let more HBM4 products qualify for Rubin GPUs, potentially boosting output, and that Samsung and SK hynix are preparing 8-Hi HBM4 for Rubin Ultra in the second quarter of 2027 instead of the planned 12-Hi HBM4E. Fewer DRAM dies per stack lowers cost per stack and the bill of materials, and lets the same bit output support more GPUs. Qualification breadth, not peak speed, is what the ramp needs.

Next Up

The immediate test is availability rather than specification. Oracle said on October 27 that it plans HGX Rubin NVL8 with two 64 core Intel Xeon 6 CPUs, 4TB of DDR5 and 6.4 Tbps of RDMA networking, and will expand OCI Superclusters to multi gigawatt scale. Google Cloud has promised broader general availability in November, and CoreWeave already runs production workloads. How those deployments behave under real agentic traffic will settle the argument that the trimmed numbers do not matter.

Longer term, attention shifts to Rubin Ultra and its 8-Hi HBM4 transition in the second quarter of 2027, and to whether AMD converts its paper advantage into shipped Helios volume. NVIDIA says it publishes pareto performance on named models and real agentic configurations, which invites exactly the third party auditing that produced this story. The next revision will be read the same way.