TSMC and Samsung Sign On to ASML High NA EUV as the AI Chip Arms Race Accelerates

On September 8, 2026, Samsung Electronics and TSMC announced commitments to adopt ASML's High NA EUV lithography systems, with Samsung planning to use the machines for DRAM production starting in 2028 and TSMC expecting to apply them to advanced logic chips from 2030. The announcements bring the world's two largest chipmakers alongside Intel as customers for ASML's most advanced and most expensive manufacturing equipment, and they give ASML a concrete answer to the question that has hung over its business for more than a year: will anyone beyond Intel actually buy these tools at scale.

Key Facts

CNBC reported on September 8 that Samsung, one of the world's biggest memory chipmakers, will use ASML's High NA EUV machines to produce DRAM from 2028, an industry first for memory production. Samsung said the adoption would extend its DRAM scaling roadmap and make the process more efficient, and CNBC noted the move marks the first time a memory maker has committed the technology to high volume DRAM manufacturing.

CNBC reported on September 8 that TSMC expects to adopt High NA EUV for advanced chips from 2030, with the company saying use of the machines will rise primarily because of the increasingly complex transistor architectures required for AI applications. That timeline places TSMC's production deployment two years behind Samsung's memory ramp and roughly four years behind Intel, which has been using the tools since July 2026.

CNBC reported on September 8 that each High NA EUV machine costs about $400 million, making them among the most expensive pieces of production equipment ever sold to the semiconductor industry. ASML's EUV lithography systems print circuit patterns onto silicon wafers, and the High NA generation can print smaller and more intricate patterns than its predecessor.

CNBC reported on September 8 that TSMC and Samsung will also join ASML in an industry initiative to advance next-generation 12-inch photomask technology, upgrading from the current 6-inch format. Photomasks are effectively the stencils used to print patterns onto wafers, and ASML said the benefits of a larger mask include better productivity and lower chipmaking costs.

TrendForce reported on September 7 that ASML and partners launched that collaborative 12-inch photomask initiative, targeting a 12-inch mask pilot line for 2031 with High NA production at advanced nodes expected by about 2033. Business Insider carried related reporting on September 8, and ASML issued its own press release on September 8 confirming the customer commitments.

CNBC reported on September 8 that ASML says it will add about 30 percent EUV capacity in 2027, that ASML stock is up about 120 percent over the past year, and that Barclays called the announcements a positive in a note published on Tuesday. Barclays wrote that the commitments should provide more visibility on adoption, which has been a key debate, and that demand is clearly strong.

Analysis

The bigger picture here is that ASML needed exactly this kind of validation. High NA EUV has been a hugely expensive bet for the company, and Intel's early adoption in July 2026 was not enough on its own to prove the market, especially given Intel's well documented struggles in advanced manufacturing over the past several years. By locking in Samsung for 2028 and TSMC for 2030, ASML turns a single customer story into a broad industry roadmap, which is precisely the signal investors needed to justify a stock that had already risen about 120 percent in a year. Barclays framed the news as giving ASML more visibility into its own planning, and the analyst note points to a significant decision ahead on whether to expand EUV capacity beyond the targets the company has already announced.

What this really means is that the two customers are making very different bets on timing and on the technology itself. Samsung's choice to put High NA EUV into DRAM production in 2028 is the more aggressive and arguably the more surprising decision, because memory patterns are regular and repetitive, which makes them a more tractable first target for a brand new lithography system than the tangled, irregular transistor layouts of leading edge logic. TSMC's 2030 timeline for advanced logic is more cautious and suggests the company intends to squeeze additional value from its existing EUV and low NA tools before committing the most expensive machines in the industry to its hardest manufacturing problem. Intel, by contrast, is already using the tools, which gives it a head start in learning the technology but also means it is absorbing the risk and cost of being first.

The push toward larger 12-inch photomasks reinforces the same underlying logic. Bigger masks mean more die per exposure, better productivity, and lower cost per chip, but they require the entire ecosystem, mask shops, pellicles, inspection tools, and lithography hardware, to retool together. That kind of coordinated industry shift tends to favor the largest and best capitalized players, because they can absorb the transition costs and spread them across enormous production volumes. Smaller chipmakers may find the bar rising just as the leading edge moves further away, which is a quiet but important consequence of today's announcements.

Why It Matters

The AI boom has created enormous demand for chips with more transistors packed into smaller areas, and lithography is the bottleneck that determines how far transistor scaling can go. High NA EUV is the tool that lets chipmakers print the smaller, more intricate patterns that next-generation AI accelerators and memory require, which is why the price tag of roughly $400 million per machine has not scared off the companies that need them most. ASML's plan to add about 30 percent EUV capacity in 2027 is a direct bet that this demand curve keeps climbing, and today's commitments from Samsung and TSMC are the evidence that the bet is well placed.

The announcements also carry geopolitical weight. TSMC and Samsung fabricate the overwhelming majority of the world's most advanced chips, and their decisions about which lithography tools to buy shape where leading edge manufacturing can happen and at what cost. With Intel, Samsung, and TSMC all now committed to High NA EUV, the technology becomes the shared foundation of the next era of chipmaking, and the 12-inch photomask initiative points toward a 2031 pilot line and High NA production at advanced nodes around 2033. For anyone watching the semiconductor industry, the practical question is no longer whether High NA EUV will be adopted, but how quickly each company can turn a $400 million machine into working chips that customers actually buy.

Next Up

The most immediate milestones are the production ramp dates the companies have now committed to publicly. Samsung's DRAM deployment in 2028 is the nearest target, and it will be the first real test of whether High NA EUV can deliver the yield and cost improvements in memory that ASML has promised. TSMC's advanced logic adoption in 2030 gives the company time to watch Samsung and Intel work through the inevitable early production issues before committing its own fabs.

Between now and those dates, watch for ASML to make a decision on whether to expand EUV capacity beyond the roughly 30 percent increase it has already outlined for 2027, a call that Barclays explicitly flagged as significant given how strong demand appears. The 12-inch photomask pilot line targeted for 2031 and the broader industry effort around it will also move forward in stages, and each step will tell observers whether the larger mask format is on track to deliver the cost savings ASML has described. For ASML shareholders, the multi-year visibility from this week's announcements is the headline; for the chip industry, the clock is now running on promises that will take the better part of a decade to fulfill.