TSMC has informed its largest supply-chain partners that its N2 2-nanometer process has crossed a 70% defect-free die yield, a milestone that has historically taken two quarters longer than the company's public roadmap suggested. The disclosure, made in a private call with Apple, Qualcomm, and MediaTek, sets up a faster ramp than the industry had assumed.
Why 70% Matters
At 70% yield, a wafer's cost per usable die crosses the threshold at which the process becomes economically attractive for premium-tier mobile parts. Apple had originally scheduled the A19 Pro for the second half of 2027; the new yield figure allows TSMC to bring the ramp forward to Q1 2027, two quarters earlier. Qualcomm's Snapdragon 8 Gen 5 and MediaTek's Dimensity 9500 are likely to follow on a similar schedule.
「This is the cleanest node ramp TSMC has done since N7,」 said one executive at a top fabless customer who was on the call. 「We were skeptical when they said Q4 of last year, but the data now backs it up.」
What It Means for the Rest of the Industry
Samsung Foundry's competing 2nm gate-all-around process is still in low-volume production with reported yields in the 30-40% range. Intel 18A is on a different cadence and serves primarily Intel's own products plus a small set of foundry customers. A clean TSMC 2nm ramp effectively resets the performance-per-watt lead the company has held since 5nm, and lengthens it by at least one product cycle.
The Catch
The yield milestone does not solve TSMC's capacity problem. N2 wafer starts remain constrained through the end of 2027, and Apple is still the anchor customer taking the majority of available output. The downstream effect is that competing flagship phones from Chinese OEMs are likely to remain on a refined 3nm process for an extra generation, widening the silicon gap in the premium tier.
TSMC declined to comment on the disclosure. Apple did not respond to a request for comment.
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